Senior Design Verification Engineer (hiring a team of 3-4 engineers)
Full Time
San Jose, CA 95113
$130,000 - $170,000 a year
Posted
Job description
Job Title: Senior Design Verification Engineer
Location: San Jose, CA (onsite) or 100% remote from any US location
Openings: 3-4, ideally looking to hire a collocated team
Status: US Citizen or US Permanent Resident only
Full-time: Salary + Benefits + Bonuses or Contractor
Responsibilities:
As a senior member of an SOC development team, you would be responsible for driving the Design Verification of ARM based SoCs. You will leverage your Functional Verification experience to develop Verification plans, create environments and tests to stress the correctness and effectiveness of design features. If you have Design Verification experience building SystemVerilog/UVM-based environments and stimulus, directing random testing and deploying a coverage-based approach, joining the Encore Semi Verification team could be for you.
Qualifications:
-
The anticipated compensation for this position is between $130,000.00 - $170,000.00 and based on a full-time schedule. Your ultimate compensation may vary as we carefully consider a wide range of factors, including customer assignment, your job-related skills, qualifications, experience and location.
-
Location: San Jose, CA (onsite) or 100% remote from any US location
Openings: 3-4, ideally looking to hire a collocated team
Status: US Citizen or US Permanent Resident only
Full-time: Salary + Benefits + Bonuses or Contractor
Responsibilities:
As a senior member of an SOC development team, you would be responsible for driving the Design Verification of ARM based SoCs. You will leverage your Functional Verification experience to develop Verification plans, create environments and tests to stress the correctness and effectiveness of design features. If you have Design Verification experience building SystemVerilog/UVM-based environments and stimulus, directing random testing and deploying a coverage-based approach, joining the Encore Semi Verification team could be for you.
Qualifications:
- Proficient in Verilog and SystemVerilog
- Experience with functional Design Verification of ASICs and SoCs
- Ability to write a testplan and executing on it, writing tests and driving functional coverage
- Strong experience with SystemVerilog for Verification as well as experience with UVM environments
- Strong debugging experience
- Knowledge of other languages used in Verification which could include Verilog, C/C++ tests, or scripting languages such as Python
- Experience with complex SoCs using ARM cores and high speed interfaces such as PCIe would be a plus
- BSEE with 7+ years of experience as a Verification Engineer
-
The anticipated compensation for this position is between $130,000.00 - $170,000.00 and based on a full-time schedule. Your ultimate compensation may vary as we carefully consider a wide range of factors, including customer assignment, your job-related skills, qualifications, experience and location.
-
johnandkristie.com is the go-to platform for job seekers looking for the best job postings from around the web. With a focus on quality, the platform guarantees that all job postings are from reliable sources and are up-to-date. It also offers a variety of tools to help users find the perfect job for them, such as searching by location and filtering by industry. Furthermore, johnandkristie.com provides helpful resources like resume tips and career advice to give job seekers an edge in their search. With its commitment to quality and user-friendliness, johnandkristie.com is the ideal place to find your next job.